时钟修改

vim arch/arm/cpu/arm920t/start.S

# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)        ldr     r1, =0x3ff        ldr     r0, =INTSUBMSK        str     r1, [r0]                /* FCLK:HCLK:PCLK = 1:2:4 */        /* default FCLK is 120 MHz ! */        ldr     r0, =CLKDIVN        mov     r1, #5        str     r1, [r0]        /* add by Flinn */                #define S3C2440_MPLL_200MHZ     ((0x5c<<12)|(0x01<<4)|(0x02))                #define S3C2440_MPLL_400MHZ     ((0x5c<<12)|(0x01<<4)|(0x01))        mrc     p15, 0, r1, c1, c0, 0           orr     r1, r1, #0xc0000000        mcr     p15, 0, r1, c1, c0, 0        /* MPLLCON = S3C2440_MPLL_400MHZ */        ldr r0, =0x4c000004        ldr r1, =S3C2440_MPLL_400MHZ        str r1, [r0]

SDRAM设置

vim board/samsung/smdk2440/lowlevel_init.S    #define REFCNT                  1113   -> 0x4f4

时钟前面设置了， 删除后面的

vim board/samsung/smdk2440/smdk2440.cboard_early_init_f（）：#if 0            /* to reduce PLL lock time, adjust the LOCKTIME register */            writel(0xFFFFFF, &clk_power->locktime);                /* configure MPLL */            writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,                   &clk_power->mpllcon);                /* some delay between MPLL and UPLL */            pll_delay(4000);                /* configure UPLL */            writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,                   &clk_power->upllcon);#endif

再次烧写

U-Boot 2014.10 (Nov 01 2018 - 11:06:54)                        CPUID: 32440001            FCLK:      400 MHz            HCLK:      100 MHz            PCLK:       50 MHz            DRAM:  64 MiB            WARNING: Caches not enabled            Flash: *** failed ***            ### ERROR ### Please RESET the board ###

原因是

board_init_r                flash_init 此时我们的nor flash还不识别                去掉                else {                    puts(failed);                    //hang();                }

重新编译烧写

U-Boot 2014.10 (Nov 01 2018 - 11:14:31)        CPUID: 32440001        FCLK:      400 MHz        HCLK:      100 MHz        PCLK:       50 MHz        DRAM:  64 MiB        WARNING: Caches not enabled        Flash: *** failed ***        *** Warning - bad CRC, using default environment                In:    serial        Out:   serial        Err:   serial        Net:   CS8900-0        Error: CS8900-0 address not set.                Warning: Your board does not use generic board. Please read        doc/README.generic-board and take action. Boards not        upgraded by the late 2014 may break or be removed.